Method for forming a copper interconnect using a multi-platen chemical mechanical polishing (CMP) process

ABSTRACT

A copper interconnect polishing process begins by polishing ( 17 ) a bulk thickness of copper ( 63 ) using a first platen. A second platen is then used to remove ( 19 ) a thin remaining interfacial copper layer to expose a barrier film ( 61 ). Computer control ( 21 ) monitors polish times of the first and second platen and adjusts these times to improve wafer throughput. One or more platens and/or the wafer is rinsed ( 20 ) between the interfacial copper polish and the barrier polish to reduce slurry cross contamination. A third platen and slurry is then used to polish away exposed portions of the barrier ( 61 ) to complete polishing of the copper interconnect structure. A holding tank that contains anti-corrosive fluid is used to queue the wafers until subsequent scrubbing operations ( 25 ). A scrubbing operation ( 25 ) that is substantially void of light is used to reduce photovoltaic induced corrosion of copper in the drying chamber of the scubber.

FIELD OF THE INVENTION

[0001] The present invention relates generally to semiconductormanufacturing, and more particularly to, forming a copper/tantaluminterconnect over an integrated circuit (IC) using a multiple-platen CMPprocess.

BACKGROUND OF THE INVENTION

[0002] In the integrated circuit (IC) industry, lithographicallypatterned and etched aluminum interconnects are now being replaced withmore advanced inlaid copper interconnects. While copper interconnectsoffer significant advantages over aluminum interconnects, such asimproved electromigration resistance and reduced resistivity, the use ofcopper interconnects is exposing various unique problems in the ICindustry. For example, barrier materials were not needed for aluminuminterconnects. However, for copper, the industry has generallydetermined that barrier materials are required in order to make a highyielding copper interconnect that are reliable. Generally, tantalumbarrier layers have become an optimal choice for barrier materials whencreating copper interconnects. However, tantalum material requires amuch different polishing slurry than copper material, whereby new crosscontamination issues now exist between platens of a copper interconnectCMP system. Such contamination issues did not exist for aluminuminterconnects.

[0003] In addition, it has been difficult to achieve improved planarityand reduced defectivity in many copper CMP interconnect processes. Also,due to the presence of more layers within a copper interconnectstructure as compared to an aluminum interconnect structure, thethroughput of copper processing needs further improvement. In addition,copper has proven to be a more environmentally sensitive material in anintegrated circuit fabrication facility whereby adverse corrosion anddefects due to ambient exposure and exposure to light has createdcertain unique manufacturing problems which now need to be addressed bythe industry. These unique problems were not at issue in previousaluminum CMP processes and cannot be adequately dealt with by adoptingpreexisting aluminum CMP techniques.

[0004] As an example of the lack of compatibility with aluminum CMP andcopper CMP, aluminum materials do not require polishing via severaldifferent chemically incompatible slurries whereby cross contaminationbetween slurries becomes an issue. In addition, corrosive effects onaluminum when exposed to an ambient environment or to light arenon-existent. Further, the aluminum buffing or polishing processes usedpreviously in the art to perfect surface topographies in aluminuminterconnects have been shown to cause significant leakage current incopper devices due to the presence of potassium. Also, the pH shock ofthese preexisting aluminum CMP slurries is non-optimal for use in copperprocessing. In fact, some prior art aluminum and copper CMP processesare adjusted to a pH range which results in significant and adversecorrosion of the copper interconnect over time. Reduction of coppercorrosion is clearly desired in the industry.

[0005] Therefore, there exists in the industry a need for an improvedCMP chemical mechanical polishing (CMP) process.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006]FIG. 1 illustrates, in a flow chart, a high level process flowthat is used to form a plurality of stacked inlaid copper interconnectsover an integrated circuit (IC) substrate.

[0007]FIG. 2 illustrates, in a flow chart, a two-step method ofpolishing an inlaid structure within the process of FIG. 1.

[0008]FIG. 3 illustrates, in a flow chart, a three-step method forpolishing a copper inlaid structure within the process of FIG. 1.

[0009] FIGS. 4-9 illustrate, in cross-sectional diagrams, integratedcircuit structures represented at various stages of processing inaccordance with FIGS. 1-3.

[0010] It will be appreciated that for simplicity and clarity ofillustration, elements illustrated in the drawings have not necessarilybeen drawn to scale. For example, the dimensions of some of the elementsare exaggerated relative to other elements for clarity. Further, whereconsidered appropriate, reference numerals have been repeated among thedrawings to indicate corresponding or analogous elements.

DESCRIPTION OF A PREFERRED EMBODIMENT

[0011] Generally, FIGS. 1-9 herein teach an improved chemical mechanicalpolishing (CMP) process that may be used to form copper interconnectsover a semiconductor substrate. A “two-step” copper (Cu) and tantalum(Ta) CMP embodiment and a “three-step” copper tantalum copper CMPembodiment is taught herein via FIGS. 2 and 3 respectively. These twointerchangeable processes have been shown to provide better planarityand/or reduced defectivity in copper interconnects. In addition, thecopper polishing slurry and the tantalum barrier polishing slurry, whenused in prior art systems, would generally result in adversecross-contamination between CMP platens. The process taught hereinimplements unique rinsing operations of both the wafer and variousplatens at various stages during CMP process to reduce slurrycross-contamination.

[0012] In addition, the CMP processes taught herein is generallydesigned to reduce intrinsic potassium contamination and copper smearingalong surfaces of the interconnect structure whereby leakage currentsare reduced in copper IC structures. Furthermore, an improved holdingtank that utilizes anti-corrosive fluids as well as the implementationof light-reduced post CMP scrubbing techniques ensures that coppercorrosion on processed copper interconnects are completely prevented orat least reduced when using an embodiment taught herein. In addition, amultiple platen is coupled with a computer feed back mechanism in oneembodiment of the CMP process taught herein where such a feedbackmechanism can significantly improve wafer throughput and maintain a highlevel of throughput during CMP processing. Furthermore, the CMP slurriestaught herein are engineered within a specific range of pH in order toreduce or optimize pH shock disadvantages, interconnect contamination,and/or corrosion of copper interconnects.

[0013] Specific process details can be better understood with specificreferences to FIGS. 1-9 hereinbelow.

[0014]FIG. 1 teaches a process 10 that is used to form a plurality ofcopper-based interconnects over an integrated circuit (IC) wafer or likesubstrate. Process 10 of FIG. 1 begins by providing a substrate withinor prior to step 11. The substrate is any material on which electricalcircuitry can be formed or supported. In one form, the substrate is oneor more of a silicon wafer, a silicon on insulator (SOI) substrate,germanium material, gallium arsenide, other III-V compounds, epitaxialmaterials, silicon carbide, or like substrate materials. On top of thissubstrate material is formed various active, passive, and/or mechanicaldevices along with associated conductive interconnects. These IC devicesformed over the substrate are to be interconnected to each other and toexternal integrated circuit terminals by the copper inlaid structures.The copper inlaid structures are formed by the process specificallyillustrated via FIG. 1.

[0015] In order to enable formation of these conductive ICinterconnects, step 11 involves the deposition of dielectric materials,dielectric or organic etch stop layers, and/or antireflective coatings(ARC) for use in defining one or more inlaid structures. The inlaidstructures formed herein may be single inlaid structures, dual inlaidstructures, or other inlaid structures which are useful for connectingone electrical or mechanical device to another device over a substrate.Generally, the dielectric materials used to define inlaid structuresinclude one or more of tetraethylorthosilicate (TEOS) glass, fluorinatedTEOS, borophosphosilicate glass (BPSG), other doped oxides, spin onglasses (SOGs), dielectric organics, low k dielectrics, air regions,silicon dioxide, silicon nitride, silicon oxyntride, silicon-richsilicon nitride, refractory metal oxides, and/or like layers ofmaterial.

[0016] A typical structure resulting from the step 11 of FIG. 1 isillustrated in FIG. 4. FIG. 4 shows the IC substrate as a siliconsubstrate 40. Within the substrate 40 of FIG. 1 is shown a single activeelectrical device referred to as MOS transistor 49. The MOS transistor49 has source and drain regions 44 which contain lightly doped drainregions (LDD regions) adjacent highly doped bulk current electrodes.Halo implants, threshold adjust implants, punchthrough implants, andlike processing may also be used for the transistor 49. A channel region(un-numbered in FIG. 4) lies below a gate dielectric layer 41 so thatthe channel region is located laterally between the source and drainregions 44. A conductive gate electrode 42 above the gate dielectric 41controls a conductivity of the channel region and therefore switches theMOS transistor 49 between the on and off state depending upon variousvoltage biases. A dielectric side wall spacer 43 is formed laterallyadjacent a side wall of the gate electrode 42 to isolate the gateelectrode, form self aligned contacts to regions 44, and/or to allowself-aligned formation of the LDD regions within electrodes 44. A firstdielectric layer 45 is used to encapsulate the transistor 49 andcontains various openings which connects to the gate electrode 42 andthe current electrodes 44 (connections to layer 44 are not specificallyshown in FIG. 4 since they occur out of the cross-section of FIG. 4).The current electrodes 44 and the gate electrode 42 are connected bytungsten plug regions 51 that fill the openings in layer 45 as shown inFIG. 4. The tungsten plug 51 and/or the dielectric layer 45 are formedby chemical vapor deposition (CVD) of material followed by chemicalmechanical polishing (CMP) the result in the planar local interconnectsrequired by the IC.

[0017] The specifics of step 11 of FIG. 1, which discusses thedeposition of dielectric materials, etch stop layers, and/or ARC layersfor the inlaid structure, is then specifically illustrated by layers46-48 of FIG. 4. FIG. 4 illustrates an etch stop layer 46 which alsofunctions as an antireflective coating (ARC) during lithographicoperations. Etch stop layers and ARC layers may be formed as separatelayers or may be formed by the same layer. Generally, the etch stoplayer 46 is formed as a silicon nitride layer, a silicon oxynitridelayer, a silicon rich silicon nitride layer, composites thereof, and/ora like etch stop material. A thicker layer 47 is then formed over a topof the etch stop layer 46. Preferably, the layer 47 is a fluorinatedtetraethylorthosilicate layer (FTOS), a TEOS layer, borophosphosilicateglass (BPSG), phosphosilicate glass (PSG), a low K dielectric material,a spin on glass (SOG), a composite of any of these materials, or a likedielectric material. A photoresist layer 48 is then spin coated andpatterned over a surface of the layer 47 as shown in FIG. 4. In summaryof FIG. 4, FIG. 4 illustrates the formation of various layers referencesin step 11 of FIG. 1 where these layers are subsequently used to definean inlaid interconnect structure.

[0018] After performance of the step 11 in FIG. 1, a step 12 isperformed. In step 12, an etch process is used after the formation of amasking layer 48 where layer 48 is generally a lithographicallypatterned photoresist layer. The etch process, performed in the presenceof the masking layer 48, forms the inlaid structure as shown in FIG. 5.As previously discussed, FIG. 5 illustrates a single inlaid structure,however, it is important to note that a dual inlaid structure or anyother inlaid embodiment may be manufactured using the process of FIG. 1.In summary of FIG. 5, FIG. 5 illustrates that portions of layers 47 and46 that are exposed by the photoresist 48 are etched by a plasma orreactive ion etch (RIE) to form the inlaid formation 50 as shown in FIG.5.

[0019] After etching of the inlaid structure in step 12 in FIG. 1, abarrier material is deposited in a step 13 of FIG. 1. Generally, thebarrier material is any material that prevents subsequently formedcopper material from contaminating adjacent dielectric layers orunderlying active devices or vice versa. Barrier layers, as used herein,may be an additional layer deposited by any manner over the surface ofthe inlaid structure, may be an exposed surface portion of the inlaidstructure that is treated by diffusion, doping, thermal processing, orimplantation, to be a protective barrier region, or may be any otherregion that functions to protect the copper from the surroundingdielectric or vice versa. Deposited barrier layers that are generallyused in the industry are tantalum nitride, titanium nitride,titanium/tungsten, tungsten, tantalum, composites thereof, or the like.The integrated circuit (IC) industry is currently using tantalummaterial as a preferred barrier layer for copper interconnects where thebarrier is a few tens of angstroms to several hundred angstroms inthickness. Therefore, step 13 of FIG. 1 is used to form a tantalumbarrier layer or like barrier region over the topography of the inlaidstructure as illustrated by layer 61 in FIG. 6.

[0020] After formation of the barrier layer via step 13 of FIG. 1, astep 14 of FIG. 1 is performed. In step 14 of FIG. 1, a bulk copper filmis deposited or formed over a top of the barrier layer. The formation ofcopper within the interconnect structure is generally illustrated inFIG. 6. FIG. 6 illustrates one embodiment where the formation of a CVDseed layer 62 is first performed. A thicker copper layer 63 is thenelectroplated or electrolyses plated over a top of the copper seed layer62. In another embodiment, the layers 62 and 63 of FIG. 6 may bereplaced by a single thick CVD copper layer. Furthermore, the layers 62and 63 may be replaced by any other copper layer formed by anothermethod or a copper composite material (e.g., copper/silicon).

[0021] After formation of the bulk copper material 62 and 63 in FIG. 6,a step 15 of FIG. 1 is used to polish the layers 61-63 in FIG. 6.Generally, the polishing process represented by step 15 of FIG. 1results in a structure similar to that illustrated in FIG. 7. In FIG. 7,top portions of all three of the layers 61-63 have been polished to someextent. Specifically, the barrier layer 61 has been polished to form apolished barrier layer 71 and the copper layers 62 and 63 have beenpolished to form a copper interconnect region 72 and 73. Generally, theCMP process illustrated structurally in FIG. 7 and illustrated via aflow chart step 15 in FIG. 1 may be performed by a “two-step” processillustrated in more detail in FIG. 2 or a “three-step” CMP processillustrated and discussed in more detail with respect to FIG. 3.Discussion of the specific two-step process (FIG. 2) and discussion ofthe three-step process (FIG. 3) within step 15 of FIG. 1 is reserved forlater paragraphs.

[0022] After completion of all polishing operations of the interconnectstructure as indicated by step 15 of FIG. 1 and illustrated in FIG. 7,FIG. 1 indicates that steps 11-15 are repeated via a step 16 if step 16determines that more interconnect layers are to be formed within theintegrated circuit. Current integrated circuit (IC) devices are beingmanufactured that contain seven or eight layers of interconnectingmetallurgy over active devices. Therefore, the steps of FIG. 1 may beused to form a single interconnect layer in isolation or may be used toform eight or more stacked copper interconnect layers as are required bya specific integrated circuit design.

[0023] To illustrate the stacking of interconnects through use of theprocess of FIG. 1, FIG. 8 illustrates a semiconductor device thatcontains at least two inlaid layers formed on top of each other whereeach inlaid layer is formed via the process illustrated by FIG. 1.Specifically, FIG. 8 illustrates a single inlaid first interconnectstructure 75 previously discussed via FIGS. 4-7 and a dual inlaid secondinterconnect structure 77 that overlies the structure 75. In FIG. 8,another barrier layer 87 is formed over the first interconnect structure75. The layer 87 is generally analogous to the barrier layer 46. Overthe layer 87 is formed a thicker dielectric layer 82 which is analogousto the layer 47. A second etch stop layer and anti-reflective layer 83is formed over the layer 82 as illustrated in FIG. 8. The layer 83 isanalogous to the layer 46. Over the layer 83 is formed a thickerdielectric layer 84 which is analogous to the previously discusseddielectric layers 47 and 82. After formation of the layers 82, 83, 84,and 87, one or more lithographic and etch processes are used to form aninterconnect trench structure through the layer 84 and contact viaopenings through the layer 82 that together make a dual inlaidinterconnect structure 77.

[0024] After removal of selective portions of the layers 82, 83, 84, and87, a barrier layer 85 is deposited within the dual inlaid structure 77.As previously discussed (see FIG. 6), a copper bulk layer 81 and 86 isthen formed over a top of the barrier layer 85. The layer 86 of FIG. 8is analogous to the layer 62 of FIG. 6 and the layer 81 of FIG. 8 isanalogous to the layer 73 of FIG. 6. After formation of the layers 85,86, and 81 in FIG. 8, a chemical mechanical polishing (CMP) process, asillustrated in step 15 of FIG. 1, is used to form a dual inlaid copperinterconnect 77 as shown in FIG. 9.

[0025] Once the step 16 of FIG. 1 determines that no more interconnectlayers are required within the IC, the passiviation processing of FIG. 9is performed. FIG. 9 illustrates that the top interconnect layer 77 ispassivated with a barrier layer 91. In a preferred form, the barrierlayer 91 is a plasma enhanced nitride (PEN) layer. Over the barrierlayer 91 is formed a passivation layer 92 which is preferably a siliconnitride layer or a silicon oxynitride layer. A polyimid layer 93 is afinal passivation layer that is formed over the layer 92. The device ofFIG. 9 is then packaged into an integrated circuit package or connectedto a printed circuit board in order to form a larger electrical system.

[0026] Returning to step 15 of FIG. 1, the polishing process illustratedin step 15 in FIG. 1 is performed by one of either the two-step CMPprocess illustrated in FIG. 2 or the three-step CMP process illustratedin FIG. 3 (or some hybrid thereof).

[0027]FIG. 2 illustrates what is referred to as a “two-step” copperinterconnect polishing process that begins with a copper polishoperation (the “first step”) and ends with a tantalum polish operation(the “second step”, thus the term “two step” polish). In one form, theprocess of FIG. 2 is used to perform the polishing discussed previouslyvia step 15 of FIG. 1.

[0028]FIG. 2 begins by performing a higher speed bulk copper polish on afirst platen within a CMP system. Generally, the polishing taught hereinwas experimentally performed on an Applied Mirra CMP system which iscommercially available in the market at this time. A first platen onthis polishing system was dedicated for use as a bulk copper polishplaten as illustrated in step 17 of FIG. 2. In order to enable bulkcopper removal, this first platen was provided with a first slurry. Thefirst slurry generally comprised an alumina abrasive, an oxidizer, and acorrosion inhibitor. Specifically, the alumina abrasive used inexperimentation was a W400 alumina abrasive, the oxidizer that wasutilized in the first slurry was hydrogen peroxide (H2O2), and thecorrosion inhibitor was 1, 2, 4 triazole. In addition, ammonia citrate(NH4 citrate) is added to the first slurry as an additional complexingagent. While these specific compounds were used, any other slurrycomposition may be used as long as that CMP slurry enables a fast copperremoval rate.

[0029] In step 17 of FIG. 2, a polishing pressure of roughly 2-6 poundsper inch (psi) is applied between the wafer and the platen. In apreferred form, a polishing pressure of greater than 4 psi is used instep 17 of FIG. 2 to result in the faster copper removal rate. A platenrotational speed of 30 to 150 rotations per minute (RPM) is used in thepolishing of step 17. In addition, a slurry flow onto the platen ofroughly 50 to 500 milliliters per minute (ml/min) is utilized. Thepolishing process 17 of FIG. 2 is generally a timed polishing processwhich does not need to be optically endpointed or endpointed in anymanner. However, other embodiments of step 17 may utilize some manner ofendpoint detection to terminate the process step 17 of FIG. 2. When atimed polish is used, polishing times of roughly 30 seconds to 2 minutesare used for conventional thicknesses of the layers 86 and 81 shown inFIG. 8. A typical polishing pad that may be used for performing thepolish 17 of FIG. 2 is an IC1000 or IC1010 CMP pad manufactured byRodel.

[0030] The polish process step 17 of FIG. 2 is designed to remove asignificant top portion of the copper material 86 and 81 from thesurface of the structure illustrated in FIG. 8 at a high rate ofremoval. Generally, the step 17 of FIG. 2 is designed to result in acopper removal rate of at least 1000 angstroms per minute with removalrates of 3,000 angstroms/min to 10,000 angstroms per minute being mostlikely. Step 17 of FIG. 2 is designed to remove a substantial portion ofthe layer 81 whereby less than roughly a 2000 angstrom thickness ofcopper remains over a top of the uppermost portion of the barrier layer85 in FIG. 8.

[0031] After bulk polishing via a step 17 of FIG. 2 is complete, thewafer is removed from the first platen in a step 18. At this point, anoptional deionized (DI) water rinse or like wet clean is performed onthe wafer. This wet cleaning process is performed at a station locatedbetween the first platen and the second platen in one embodiment. Whencleaning a wafer, it has been found that the wafer cleaning stationslocated between two platens may scatter contamination onto the adjacentplatens. In the cases where such slurry cross-contamination isill-advised, an optional platen rinse may be performed in step 18 inaddition to the rinsing of the wafer. Therefore, one or more of thefirst and second platens discussed in FIG. 2 may be simultaneouslyrinsed along with the wafer in order to reduce cross contaminationbetween the first and second platen as is necessary to maintain processintegrity. In some embodiments, the first and second platens may beusing compatible slurries whereby no rinsing at all is needed betweenthe first and second platen (thus this step is optional).

[0032] After the polishing process of step 17 and the optional rinsestep 18, a slower interfacial copper polish process is begun on thesecond platen within the CMP tool. In step 19, the wafer is placed ontothe second platen where the second platen is exposed to a slurrysubstantially similar in concentration and content to that used in step17. In another embodiment, the slurry used on the first and secondplaten may be completely different from each other as long as both theseslurries are copper removal slurries. For example, the slurry used inconjunction with the first platen is likely not concerned withselectivity to the barrier layer. However, it is more likely that theslurry applied to the second platen will be engineered for a properselectivity to the barrier material. In another form, the slurry used instep 19 is identical to the slurry used in step 17 and is dispensed fromthe same reservoir.

[0033] In order to result in a slower polishing operation in step 19when compared to step 17, a polishing down force used in step 19 isgenerally less than the down force used in step 17 and ranges any wherefrom 0.5 to 4 pounds per square inch (psi). Generally, the process ofstep 19 may be altered in any manner that results in a slower polishingprocess than that used in step 17. For example, the platen rotationalspeed may be altered between steps 17 and 19 and/or a chemicalcomposition of the slurry may be changed to result in more chemicalcopper removal in step 17 when compared to step 19. Generally, the step19 is used to remove a last remaining few hundred to few thousandangstroms of copper that remains over an uppermost portion of thebarrier layer 85 within interconnect structure 77 of FIG. 8. In oneform, the polishing process of step 19 in FIG. 2 is endpointed. Theendpoint operation which is currently utilized is an optical endpointprocess which impinges an energy source onto the wafer through thepolishing pad in order to measure a reflectivity of the wafer. As thecopper is removed from the wafer over time to expose an underlyingportion of the barrier layer 85, the reflectivity of this energy sourcefrom the surface of the wafer will measurably change. Upon the detectionof this change in surface reflectivity, the polishing process can beterminated whereby optical endpoint is achieved. The polishing processof step 19 exposes a top portion of the barrier layer.

[0034] After performance of the polishing step 19, an optional rinsestep 20 is utilized. Generally, the CMP slurries used to polish coppervia step 17 and 19 is radically different and chemically incompatiblewith the chemical composition of the slurry used to subsequently polishbarrier materials. In these cases, it is advantageous to ensure thatcontamination from one copper polishing platen is not deposited on theother barrier polishing platen. To avoid this cross contamination, thewafer, upon removal from the second platen may be rinsed with deionized(Dl) water or a like wet chemistry when in transfer between the secondplaten and the third platen. In addition to rinsing the wafer, one ormore various adjacent platens (especially the second platen and/or thethird platen), may also be rinsed along with the wafer. This rinsing ofone or more of the wafer, the second platen, and/or the third platen,has been shown to significantly reduce cross contamination betweenplatens whereby copper interconnect planarity and defectivity isimproved while simultaneously increasing the throughput and reducing thedowntime of the CMP tool.

[0035] The two-step copper polishing process of steps 17 and 19 acrossthree or more different platens was performed for CMP wafer throughputreasons. If a large portion of the copper material can be removed by aCMP process having a high rate of removal via step 17, then anotherplaten may be used by step 19 to more carefully perform the moresensitive removal of the interfacial copper at the barrier-copperinterface. Therefore, while the processes taught herein may polish theentire copper material using a single platen and a single polish step inone embodiment, using the two platens for copper polishing in FIG. 2 hasadvantages. In order to maximize the throughput of the system, it isimportant to keep the polishing time of the step 17 approximately equalto the polishing time of the step 19. Specifically, it is an improvementto keep the polishing process time of step 17 and the polishing processtime of step 19 within roughly 20% variation of one another.

[0036] In another form, a robotic arm that loads wafers onto the firstplaten of the CMP machine has a fastest load time period (e.g., it maytake 30 seconds for a robotic arm to manipulate a wafer from a wafercarrier to the first platen). In these cases where throughput ismechanically limited, it is adequate for maximal throughput to simplyensure that both of the polish times for the steps 17 and 19 remainbelow this threshold period. As an example, if a robotic arm can load awafer onto the first platen every 30 seconds, it would be an improvementfor throughput to ensure that both the polish times occurring in steps17 and 19 are below 30 seconds to avoid stoppage of wafer progressthrough the system. Furthermore, if the polishing processes take longerthan the fastest load time by necessity, it is likely that throughputwill not be optimal if the polish process of step 17 takes two minuteswhile the polish process of step 19 takes fifteen seconds. In thislopsided case, it would be advantageous for throughput reasons to reducethe amount of polishing occurring at step 17 and move more burden ofpolishing to the step 19. In the above example, it would be better topolish with step 17 for 45 seconds and polish with step 19 for 45seconds as opposed to the 2 minute/15 second lopsided polish. Theequilibration or monitoring of polishing times between step 17 and step19 is important in order to maximize throughput for different lots ofwafers and process variations. Such balancing or monitoring ofcross-platen polish times prevents or reduces bottlenecks associatedwith any one platen on the polishing tool.

[0037] The balancing of the polishing times between steps 17 and 19 (orthe detection of one of these times extending beyond the mechanicalfastest load time) is performed by a step 21 of FIG. 2. In step 21 ofFIG. 2, a computer which is coupled to the CMP tool monitors a polishingtime of step 17 and also monitors the optical endpoint polishing time ofstep 19. Step 21 will then compare, via the computer, the time ofpolishing from step 17 and the time of polishing in step 19 to eachother and/or compare both these polishing times to the mechanicalthreshold time determined by the speed of wafer loading in the system.If the computer determines that appropriate tradeoffs can be madebetween the polishing time of step 17 and the polishing time of step 19to improve throughput, then the computer will either in situ change theparameters of one or more of the polishing step 17 and 19 to result insuch a change or instruct an operator or CMP engineer to make suchadjustment in a manual manner on a wafer-by-wafer or lot-by-lot manner.Changes in polish times may be accomplished by changing endpointcriterion, changing the amount of time the wafer is exposed to theplaten, or changing one or more process parameters such as platen RPM,slurry flow, down pressure, slurry composition, and/or like processparameters one or more platens.

[0038] After adjustment of the polishing times in steps 17 and 19 viathe step 21 (if any such adjustment is necessary), a barrier polishingprocess is performed in a step 22 of FIG. 2. In step 22, the wafer isplaced on a third platen and is polished using a barrier polishingslurry. Generally, the barrier polishing slurry contains a silicaabrasive, a corrosion inhibitor, and some sort of pH adjuster. In oneform, the silica abrasive can be the commercially available abrasivereferred to as SCE and provided by Cabot. In one form, the corrosioninhibitor may be 1, 2, 4 triazole, while the pH adjuster may be ammoniumhydroxide (NH4OH). It has been found pH shock, contamination, andcorrosion can be reduced when forming the copper interconnects bychanging the pH of the barrier slurry to a non-neutral pH between 2 and11. Preferably, a pH range from 8 to 9, which is fixed primarily by theammonia hydroxide, has been found to be sufficient to prevent corrosionwhen used in conjunction with greater than 2 percent of 1, 2, 4triazole. Generally, it was found that pH levels between roughly 6 and 8(near neutral) when using no triazole or triazole less then 2 percenttriazole by volume resulted in significant corrosion of copperinterconnect structures over time. Therefore, a careful adjustment ofthe pH outside of values near 7 and/or the use of greater volumes ofcorrosion inhibitors has greatly improved the reliability and yield ofcopper interconnect structures beyond that possible in the art.

[0039] A typical range used for the polishing down pressure for thebarrier polishing of step 22 is between 0.5 and 6 pounds per square inch(psi). It has been found that roughly 3 psi of polish down pressureproduces acceptable interconnect results. A typical platen speed usedfor the barrier polish in step 22 of FIG. 2 is any speed between roughly30 and 150 rotations per minute (RPM). A typical slurry flow that isused for the barrier polish in step 22 is anywhere from 50 to 500milliliters per minute (ml/min). Generally, the barrier polish 22 is atimed polish that is statically set between roughly 30 seconds and 2minutes. Of course, the polish time period depends on a thickness thatis used for the barrier layer being polished. In another form, some formof endpoint or optical endpoint may be used to terminate the barrierpolishing process in FIG. 2. A typical polishing pad that has been usedto perform barrier polishing with good results is an embossed politexpad provided by Rodel. The barrier polishing process taught herein hasbeen shown to reduce leakage between interconnect structures. It isbelieved that the polishing process taught herein has reduced potassiumcontamination along a surface of the interconnect surface after barrierpolishing is complete. This reduction in potassium contamination isbelieved to reduce leakage current between interconnect structureswhereby the yield of integrated circuits is improved and long term ICreliability is enhanced.

[0040] After the barrier polish process of step 22 in FIG. 2, anoptional wafer rinse and platen rinse is performed during wafer unloadoperations. This rinsing operation of step 23 is performed since manyCMP tools will move a wafer over other platens during the step ofunloading the wafer from the CMP system. To avoid cross contaminationbetween platens, all platens over which the wafer robotic arm willtravel and the wafer itself are optionally exposed to a rinse operationvia step 23.

[0041] After the optional rinse process represented by step 23, thewafers are placed into an unload station (holding tank) that exposed thewafer to a holding fluid. The holding fluid contains corrosion inhibitoradditives. In the prior art, the holding fluid does not containcorrosion inhibitor additives. It has been found that if the wafersremain in the unload station for extended periods of time, corrosion andcontamination of the copper layer can be extensive and IC yield isadversely reduced. Therefore, in the prior art, it is important toquickly process wafers through the unload station after barrier polishis complete. It has been found that inadvertent maintenance delays,bottlenecks in fabrication facility processing, equipment down time,human error, and other uncontrollable and/or unfortunate situations infabrication processing have resulted in many copper interconnect waferssitting too long on the unload station, whereby yield is reduced and thecost of implementing a copper process is inversely increased.

[0042] In order to smooth these bottlenecks, improve yield, reduce cost,and improve throughput of a wafer fabrication facility, a method wasneeded to provide longer shelf life for copper materials between barrierpolishing operations and wafer scrub procedures (or other criticalprocessing steps). The extension of the queue time while reducingcorrosion and contamination is the function of the step 24 illustratedin FIG. 2. By placing the wafers into a fluid holding tank that containscorrosion inhibitors such as 1, 2, 4 triazole, wafers can be maintainedfor much longer periods of time between the barrier polish step 22 andthe wafer scrub step 25. Therefore, the wafer holding tank of step 24has reduced the likelihood of corrosion and improved the feasibility ofcopper processing and mainstream integrated circuit manufacturing.

[0043] After storage in the holding tank via step 24, a step 25 of FIG.2 is utilized. In the scrubbing step 25, a scrubbing apparatus is usedthat has two brush stations. The wafer is first loaded into a firstbrush station and mechanically brushed and wet etched for roughly 15 to50 seconds. After a first brush station is complete, a second mechanicalbrush station is used to scrub the wafer via wet chemicals andmechanical agitation for yet another time period of roughly 15 to 50seconds. It is important to note that any number of mechanical stationsfrom one to many may be used to perform the scrubbing operations taughtherein. In addition, the mechanical/brush scrubbing operations taughtherein may be replaced with ultrasonic or other methods of waferscrubbing/cleaning.

[0044] After performing various ultrasonic and/or mechanical brush scruboperations, a third chamber of the scrubbing tool or a separate machineis used to dry one or more scrubbed wafers for subsequent processing.Typically, within drying processes used for aluminum interconnectprocessing and all known processes currently used for copperinterconnects, a light source has been used within the spin rinsechamber to reduce drying times and increase wafer throughput. It wasfound that the provision of a high powered light within the spin rinsechamber dried wafers much faster than without the light whereby thelight has generally become a standard in the art. However, with the useof copper interconnects, it has been found that the presence ofsubstantial amounts of light within the spin rinse and drying chamber ofthe scrub equipment is disadvantageous. Specifically, it has been foundand is believed that the light within this chamber induces aphotovoltaic effect that results in creation of corrosion across thecopper interconnects. For this reason, it has been found that a darkerspin rinse process that is substantially void of light is better for thenewer copper interconnects. While the substantial reduction and/orcomplete removal of the light from the drying chamber of the scrubbingapparatus has slightly extended drying times and impacted throughputcontrary to the desires of the prior art, it was found that theadvantages of reducing corrosion outweighed this slight lengthening ofthe drying time. In addition, the adverse impact to throughput byremoval or lack of use of the light has been reduced or eliminated byfunneling hot air onto the surface of the wafer during the spin rinsecycle. Generally, it was found that any energy source that does notinvoke or does not create a photoelectric effect on the copperinterconnects can be used to speed the drying process through thescrubbing step 25 of FIG. 2 whereby throughput can be maintained whilecorrosion is significantly reduced.

[0045] After the scrubbing of the wafer via step 25, processing of thesingle inlaid or dual inlaid structure is complete. It has been foundthat the process, discussed with respect to FIG. 2, results in improvedplanarity and reduced dishing within copper interconnects. Becausedishing and erosion are reduced, many contact vias can be placeddirectly on top of one another as illustrated in FIG. 9. In general, ithas been found that as many as seven via connections can be placed ontop of one another whereby the dishing and erosion that occurs in priorart CMP processes would render such a structure impossible to form.Therefore, there are some additional structural integrated circuitbenefits to using the chemical mechanical polishing process taughtherein that may have the advantage of reducing overall IC dimensions viaimplementation of more efficient routing of vias and interconnects.

[0046]FIG. 3 illustrates a “three step” polishing process that may beused for the step 15 of FIG. 1 in lieu of the “two step” process of FIG.2. FIG. 3 is referred to as a “three step” process since a copper polishis followed by a tantalum process which is followed by another copperpolish.

[0047] In FIG. 3, the steps 26-30 are substantially similar to thatdiscussed previously via steps 17-21 of FIG. 2. Therefore, these stepsare not addressed in detail again for FIG. 3. However, FIG. 3 differsfrom FIG. 2 via the step 31 of FIG. 3. In step 31, the wafer is exposedto a dielectric buff that removes exposed portions of the barrier layerand portions of the oxide that underlie the barrier layer. In one form,the dielectric buff step 31 uses a commercial dielectric CMP slurry suchas SC112 or SS12 available from Cabot. A typical range used for thepolishing down pressure within step 31 is between 0.5 and 6 pounds persquare inch (psi) with a pressure of about 3 being typical. A typicalplaten speed used for the barrier polish in step 31 of FIG. 3 is anyspeed between roughly 30 and 150 rotations per minute (RPM). A typicalslurry flow that is used for the step 31 is anywhere from 50 to 500milliliters per minute (ml/min). Generally, the barrier polish 31 is atimed polish that is statically set between roughly 30 seconds and 2minutes with one minute being typical. Of course, the polish time perioddepends on a thickness that is used for the barrier layer being polishedand the amount of underlying oxide/dielectric that is targeted forremoval. In another form, some form of endpoint or optical endpoint maybe used to terminate the buff step 31 in FIG. 3. A typical polishing padthat has been used to perform this buffing process with good results isan embossed polytech pad provided by Rodel.

[0048] After dielectric buffing, steps 32-34 are analogous to steps23-25 of FIG. 2. Therefore, these steps are not discussed further withrespect to FIG. 3. However, the dielectric buffing step 31 is generallydone with a silica slurry that contains potassium and does not complexcopper. It is believed that oxide potassium contamination from thisslurry adversely increases leakage currents in the final IC device. Inorder to reduce this leakage effect due to the presence of surfacepotassium, a touch up copper polish is performed by a step 35 in FIG. 3.In step 35, any alumina CMP slurry such as the exact slurry taught instep 17 of FIG. 2 for the bulk copper removal is used for the step 35 ofFIG. 3. One difference between step 17 and step 35 is that the polishingpressure of step 35 is very low (e.g., 0.2 to 0.8 psi with 0.4 to 0.5being most typical). In addition, the polishing of step 35 is very briefwhen compared to step 17 (e.g., step 35 polishes for a time period ofless than twenty seconds with ten seconds being typical). Whenincorporating the step 25, leakage current was improved in the final ICdevice.

[0049] After the touch up polish of step 35, the steps 36-38 areperformed. Steps 36-38 are analogous to the steps 32-34 of FIG. 3 or thesteps 23-25 of FIG. 2.

[0050] Although the invention has been described and illustrated withreference to specific embodiments, it is not intended that the inventionbe limited to those illustrative embodiments. Those skilled in the artwill recognize that modifications and variations may be made withoutdeparting from the spirit and scope of the invention. Therefore, it isintended that this invention encompass all of the variations andmodifications as fall within the scope of the appended claims.

What is claimed is:
 1. A method for forming an interconnect comprising:forming a dielectric layer over a semiconductor device substrate;forming an opening in the dielectric layer; forming a barrier layer overthe dielectric layer and within the opening; forming a bulk metalliclayer over the barrier layer; polishing the bulk metallic layer using afirst polish process; polishing the barrier layer using a second polishprocess wherein the second polish process includes a slurry containing apH adjusted silica abrasive, and a corrosion inhibitor.
 2. The method ofclaim 1 wherein the pH adjusted silica abrasive has a pH levelsubstantially within a range of 8 to
 11. 3. The method of claim 1wherein the pH adjusted silica abrasive has a pH level substantiallywithin a range of 2 to
 6. 4. The method of claim 1 wherein the pHadjusted silica abrasive has a pH level substantially within a range of8.0 to 9.0.
 5. The method of claim 1 wherein the pH adjusted silicaabrasive has a pH that is adjusted by the presence of ammonium hydroxidewithin the slurry.
 6. The method of claim 1 wherein the barrier layercomprises predominantly tantalum.
 7. The method of claim 1 wherein thebulk metallic layer comprises predominantly copper.
 8. The method ofclaim 7 wherein the bulk metallic layer comprising predominantly copperincludes a lower seed layer comprised of CVD copper and an upper bulkregion comprised of electroplated copper.
 9. The method of claim 1,wherein the step of polishing the bulk metallic layer comprises thesteps of: polishing a top portion of the bulk metallic layer using afirst platen that polishes at a first removal rate. polishing a bottomportion of the bulk metallic layer that underlies the top portion of thebulk metallic layer using a second platen that polishes at a secondremoval rate that is less than the first removal rate.
 10. The method ofclaim 9, further comprising rinsing the semiconductor device substrateafter polishing the top portion of the bulk metallic layer and beforepolishing the bottom portion of the bulk metallic layer.
 11. The methodof claim 9, wherein rinsing the semiconductor device substrate isperformed after polishing the bottom portion of the bulk metallic layer.12. The method of claim 9 wherein: polishing the top portion of the bulkmetallic layer includes using a first polishing down force of 2-6 psi;and polishing the bottom portion of the bulk metallic layer includesusing a second polishing down force of 0.5-4 psi, wherein the secondpolishing down force is less than the first polishing down force. 13.The method of claim 9, wherein polishing the top portion of the bulkmetallic layer is a timed polish process and polishing the bottomportion of the bulk metallic layer is optically endpointed.
 14. Themethod of claim 9, wherein the first platen uses a slurry that containsan abrasive, an oxidizer, and a corrosion inhibitor.
 15. The method ofclaim 14, wherein the first platen uses a slurry that contains analumina abrasive as the abrasive, hydrogen peroxide as the oxidizer, and1, 2, 4 triazole as the corrosion inhibitor.
 16. The method of claim 9,wherein the first and second removal rates are compared to each otherand the first and second removal rates are occasionally adjusted byprocess changes in response thereto.
 17. The method of claim 1, whereinpolishing the bulk metallic layer comprises: polishing a top portion ofthe bulk metallic layer on a first platen; polishing a bottom portion ofthe bulk metallic layer on a second platen; and polishing the barrierlayer on a third platen.
 18. The method of claim 17, further comprisingrinsing the semiconductor device substrate after polishing the bottomportion of the bulk metallic layer and before polishing the barrierlayer.
 19. The method of claim 18, further comprising rinsing the secondand third platen.
 20. The method of claim 1, wherein the slurrycomprises at least approximately 2% 1, 2, 4 triazole by volume as thecorrosion inhibitor.
 21. The method of claim 1 wherein the slurrycomprises ammonium hydroxide.
 22. The method of claim 1 furthercomprising placing semiconductor device substrate into a holding tank,wherein the holding tank contains a metal corrosion inhibitor.
 23. Themethod of claim 1 further comprising: placing the semiconductor devicesubstrate into a scubber after polishing the barrier layer; cleaning thesemiconductor device substrate within the scrubber; and drying thesemiconductor device substrate after cleaning the semiconductor devicesubstrate, wherein drying is performed in an environment that issubstantially void of visible light.
 24. A method for forming aninterconnect comprising: forming a copper containing interconnect over asemiconductor device substrate, wherein forming the copper-containinginterconnect includes removing portions of a copper containing layerusing a polishing process; cleaning the semiconductor device substrateusing a wet cleaning process; and drying the semiconductor devicesubstrate after cleaning the semiconductor device substrate, whereindrying is performed in an environment that is substantially void ofvisible light.
 25. The method of claim 24, wherein drying thesemiconductor device substrate further comprises rotating thesemiconductor device substrate about a central axis of the semiconductordevice substrate.
 26. The method of claim 24 wherein drying thesemiconductor device substrate further comprises flowing heated airacross a surface of the semiconductor device substrate while rotatingthe semiconductor device substrate.
 27. The method of claim 24 whereindrying the semiconductor device substrate further comprises applying anenergy source to the semiconductor device substrate, and wherein theenergy source does not induce a photovoltaic effect on the interconnect.28. The method of claim 24, wherein cleaning further comprisesultrasonically cleaning the semiconductor device substrate.
 29. Themethod of claim 24 wherein cleaning further comprises mechanicallyscrubbing the semiconductor device substrate
 30. A method for forming ainterconnect comprising: forming a barrier layer over a semiconductordevice substrate; forming a bulk metal layer over the barrier layer;placing the semiconductor device substrate onto a first platen;polishing the bulk metal layer using a first platen; removing thesemiconductor device substrate from the first platen; rinsing the firstplaten, a second platen, and the semiconductor device substrate afterremoving the semiconductor device substrate from the first platen andbefore placing the semiconductor device substrate onto a second platen;placing the semiconductor device substrate onto the second platen andpolishing the barrier layer using the second platen.
 31. The method ofclaim 30 wherein one of either the first platen or the second platensupports polishing using an alumina abrasive and the other another ofthe first platen or the second platen supports polishing using a silicaabrasive.
 32. The method of claim 30 wherein one of either the firstplaten or the second platen supports polishing using a slurry with afirst pH and another of the first platen or the second platen supportspolishing using a slurry with a second pH wherein the first pH isdifferent from the second pH.
 33. A method for forming an interconnectcomprising: forming a metal interconnect material over a surface of awafer; polishing a first portion of the interconnect using a firstplaten and a first polish process; polishing the second portion of theinterconnect using a second platen and a second polish process;comparing a first platen polish time to second platen polish time andadjusting an ending polish time of at least one of the first polishprocess and the second polish process in response to comparing.
 34. Themethod of claim 33, wherein the ending polish time of at least one ofthe first polish process and the second polish process are occasionallyadjusted to be substantially equal to each other over time.
 35. Themethod of claim 33 wherein a downforce pressure of one of either thefirst or second polish process is changed in response to the step ofcomparing.
 36. The method of claim 33 wherein a slurry flow rate of oneof either the first or second polish process is changed in response tothe step of comparing.
 37. The method of claim 33 wherein the platenmovement speed of one of either the first or second polish process ischanged in response to the step of comparing.
 38. The method of claim 33wherein the interconnect is a copper interconnect.
 39. The method ofclaim 33 wherein the polishing rate of one of either the first polishprocess or the second polish process are occasionally adjusted inresponse to the step of comparing.
 40. The method of claim 33 whereinthe first polish process removes interconnect material at a ratesubstantially greater than a removal rate in the second polishingprocess.
 41. A method for forming a interconnect comprising: forming ainterconnect material over a semiconductor substrate, the interconnectmaterial comprising a top bulk metal layer and a lower barrier layer;polishing an upper portion of the bulk metal layer at a first removalrate using a first platen; polishing a lower portion of the bulk metallayer at a second removal rate using a second platen wherein the firstremoval rate is greater than the second removal rate; and polishing thebarrier layer using a third platen.
 42. The method of claim 41 whereinthe interconnect material comprises primarily copper overlying atantalum-containing barrier layer.
 43. The method of claim 41 whereinthe second platen supports an alumina slurry and the third platensupports an alumina slurry.
 44. A method for forming a interconnectcomprising: forming a dielectric layer over a semiconductor devicesubstrate; forming an opening in the dielectric layer; forming a barrierlayer over the dielectric layer and within the opening; forming a bulkmetallic layer over the barrier layer; polishing a first portion of thebulk metallic layer using a first polish process; polishing a secondportion of the bulk metallic layer using a second polish process;polishing the barrier layer and a first exposed portions of thedielectric layer using a third polish process wherein the third polishprocess is further characterized as a dielectric buff process; polishinga remaining portion of the bulk metallic layer and a second exposedportion of the dielectric layer using a fourth polish process.
 45. Themethod of claim 44 wherein the barrier layer comprises predominantlytantalum.
 46. The method of claim 44 wherein the bulk metallic layercomprises predominantly copper.
 47. The method of claim 44 wherein thebulk metallic layer comprising predominantly copper includes a lowerseed layer comprised of CVD copper and an upper bulk region comprised ofelectroplated copper.
 48. The method of claim 44, wherein the step ofpolishing the bulk metallic layer comprises the steps of: polishing afirst portion of the bulk metallic layer using a first platen thatpolishes at a first removal rate. polishing a second portion of the bulkmetallic layer that underlies the top portion of the bulk metallic layerusing a second platen that polishes at a second removal rate that isless than the first removal rate;
 49. The method of claim 48, furthercomprising rinsing the semiconductor device substrate after polishingthe first portion of the bulk metallic layer and before polishing thesecond portion of the bulk metallic layer.
 50. The method of claim 44,wherein rinsing the semiconductor device substrate is performed afterpolishing the second portion of the bulk metallic layer.
 51. The methodof claim 44 wherein: polishing the first portion of the bulk metalliclayer includes using a first polishing down force of 2-6 psi; andpolishing the second portion of the bulk metallic layer includes using asecond polishing down force of 0.5-4 psi, wherein the second polishingdown force is less than the first polishing down force.
 52. The methodof claim 44, wherein polishing the top portion of the bulk metalliclayer is a timed polish process and polishing the bottom portion of thebulk metallic layer is optically endpointed.
 53. The method of claim 48,wherein the first platen uses a slurry that contains an abrasive, anoxidizer, and a corrosion inhibitor.
 54. The method of claim 48, whereinthe first platen uses a slurry that contains an alumina abrasive as theabrasive, hydrogen peroxide as the oxidizer, and 1, 2, 4 triazole as thecorrosion inhibitor.
 55. The method of claim 48, wherein the first andsecond removal rates are compared to each other and the first and secondremoval rates are occasionally adjusted by process changes in responsethereto.
 56. The method of claim 44, wherein polishing barrier layer isperformed using a third platen.
 57. The method of claim 56, furthercomprising rinsing the semiconductor device substrate after polishingthe second portion of the bulk metallic layer and before polishing thebarrier layer.
 58. The method of claim 57, further comprising rinsingthe second and third platen.
 59. The method of claim 44 furthercomprising placing semiconductor device substrate into a holding tank,wherein the holding tank contains a metal corrosion inhibitor.
 60. Themethod of claim 44 wherein polishing a remaining portion of the bulkmetallic layer includes using a fourth platen.
 61. The method of claim60 wherein polishing the remaining portion removes the bulk metalliclayer at removal rate that is less than a bulk metallic layer removalrate of the second polish process.
 62. A method for forming a metallicinterconnect comprising: forming the metallic interconnect over asemiconductor substrate using a polishing process; storing thesemiconductor substrate having a metallic interconnect in a holding tankthat contains fluid, the fluid containing a copper corrosion inhibitor;and removing the semiconductor substrate from the holding tank forsubsequent processing.
 63. The method of claim 62, wherein the inhibitoris further characterized as 1, 2, 4 triazole.
 64. The method of claim62, wherein the holding tank is periodically refreshed at intervals in arange of approximately 2-24 hours.